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Technical Program Manager , Silicon Operations

Amazon Sunnyvale, California, United States


No Relocation

Posted: August 4, 2026

Additional Content

Description
  • Leo is Amazon’s low Earth orbit satellite broadband network. Its mission is to deliver fast, reliable internet to customers and communities around the world, and we’ve designed the system with the capacity,
Description
  • Leo is Amazon’s low Earth orbit satellite broadband network. Its mission is to deliver fast, reliable internet to customers and communities around the world, and we’ve designed the system with the capacity, flexibility, and performance to serve a wide range of customers, from individual households to schools, hospitals, businesses, government agencies, and other organizations operating in locations without reliable connectivity. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Amazon Leo team is looking for a Business Operations Manager to support business and engineering stakeholders in selecting, developing and managing business relationships with critical technology and service suppliers, and others as needed to execute on Amazon Leo objectives. The ideal candidate will have a successful track record developing and executing strategy, and managing supplier performance. Experience working in new and ambiguous environments while solving complex problems with a broad range of cross functional stakeholders will be an advantage. Key job responsibilities Own the NPI-to-sustaining transition for ASIC programs, defining readiness criteria and driving cross-functional teams (Design, Test, Manufacturing, Quality, Supply Chain) through program ramp-up milestones Lead dual-source qualification end-to-end — manage sample builds, reliability testing, correlation analysis, and production validation to ensure supply resilience for all sustaining ASIC chips Navigate the full silicon development lifecycle (RTL → tape-out → bring-up → characterization → production) and coordinate sustaining activities with silicon revisions, ECOs, and errata management Align ASIC sustaining deliverables with device-level PDP gates (EVT, DVT, PVT, MP), partnering with hardware TPMs to synchronize schedules across satellite and ground terminal programs Drive sustaining KPIs (yield, DPPM, OTD, cost), manage EOL planning, and conduct business reviews with foundry and OSAT partners Build scalable mechanisms and reporting cadences to provide executive visibility into sustaining program healt
Basic Qualifications
  • - 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience - 7+ years of digital design in communication systems experience - 7+ years of full-custom analog or RF layout experience - 7+ years of wireless communications systems and implementation experience - 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience - 7+ years of verification in communication systems experience - 5+ years of UVM, C, System C, and scripting experience - 3+ years of emulation experience - Bachelor's degree in Electrical Engineering or a related field - Knowledge of UVM and Matlab - Knowledge of implementing chips with multiple power islands and power gating - Knowledge of multiple access systems including OFDMA, TDMA, and CDMA - Knowledge of end-to-end network system architecture from wireless physical layer to application endpoints - Knowledge of serial protocols including SPI, I2C, I3C, and UART - Knowledge of Python and Embedded C programming - Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems or RF engineering - Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards - Experience leading or solely developing methodology and scripts for physical synthesis - Experience taping out chips that have gone into high volume production - Experience developing products for volume production - Experience low power design techniques - Experience delivering products to volume production - Experience in modem L1/L2 algorithms development and architectures - Experience in developing link and system level simulators using MATLAB, Python, or C++ - Experience in test setup automation using MATLAB, Python, or Pearl - Experience with Agile, TDD, BDD, CI, and Git - Experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors - Experience leading technical initiatives and key deliverables - Experience with version control systems and CI/CD pipeline implementation - Experience in Bare Metal Environment development, including linker scripts, page tables and NVIC
Preferred Qualifications